Relative to microprocessors with CISC architecture, RISC microprocessors have the advantage of possessing simplified architecture, which produces notably higher execution speeds, and employing code compilers notably simpler than CISC microprocessors. In contrast, programs written for microprocessors with RISC architecture are notably more capacious, typically by 20 to 50%. The result is an increase in the loading time for a program in view of its execution, an increase in the memory resources necessary for saving the program, and an increase in the necessary bandwidth if the program must be transmitted over a network within a predetermined period.
By way of a solution to this problem, U.S. Pat. No. 5,764,994 (which is incorporated by reference) proposes applying compression processes such as Lempel-Ziv by such microprocessors to the executable code, based on the detection of repetitions of patterns, the compressed code then being decompressed on the fly at the moment of its execution by the microprocessor. All the same, such a code is difficult to be compressed due to the presence in the instructions of executable RISC code of redundant fields which contain no information, but reduce the efficacy of the data model constructed during compression. In addition, the instructions of executable RISC code have different formats, and utilize numerous registers and literal values, which make detection of repeated patterns in the code difficult.
U.S. Pat. Nos. 6,618,506 and 6,199,126 (which are incorporated by reference) provide decomposing the executable program to be compressed into two subsets respectively comprising the field of operating code and the operating field of each instruction, then conducting statistical analysis of each subset to evaluate frequencies of appearance of symbols. Next, each symbol is attributed a code whereof the size is smaller for those symbols having a high frequency of appearance in the subset, and a correspondence table between the symbols and the codes attributed to the symbols is made. Each code comprises a prefix associated with either an index or the value of the symbol according to the value of the prefix. In the case where the prefix is followed by an index, the prefix designates a group of symbols in the correspondence table and the index specifies the position of the corresponding symbol in the group. Finally, each field of instructions of the executable code is replaced by the corresponding code such as specified in the correspondence table to obtain the program in compressed form.
To optimize the memory space occupied by the compressed program, the codes of variable length are saved one after another without being aligned on memory words. To be able to be decompressed on the fly from an instruction address required by the microprocessor, the program is compressed by blocks of 64 octets (16 instructions of 32 bits), and an index table is generated for directly accessing each compressed block.
This solution may not be optimum in terms of occupation of memory. In fact, it is necessary for each block of compressed instructions to be aligned with the memory words of the addressing space, which leaves at the end of each block unoccupied locations all the greater if the selected blocks are large or all the more numerous if the selected blocks are small. In addition, the index table is relatively voluminous since it occupies 32 bits (4 octets) per block of 64 octets, which significantly penalizes the efficacy of compression.
Further, this solution may degrade performances in terms of speed of execution of the program. This degradation comes from the fact that the compressed instructions are variable in size and thus it is not possible to decompress an instruction of a block prior to having determined the length of the preceding compressed instruction. This solution thus does not conduct certain decompression operations in parallel.